A Square and Triangle Wave VCO. Part II – Taming the Voltage Spikes.

Continuing from part I, we will investigate and fix the voltage spikes on the triangle wave by using decoupling capacitors and by hacking the breadboard to drastically reduce the parasitic inductance of the connection between the two ground rails.

We will see that there is a sharp pulse of current of width about 100 ns when the MOSFET switches on, which induces a voltage spike between the supply rails due to the inductance of wires in the current’s path.

In fact, there is no reason to have such quickly changing signals in an analogue circuit running at 75 kHz, even taking into account the higher harmonics of the square wave, which are significantly suppressed due to its gently sloping edges. The smart solution to attenuating the spikes is to first smooth out the current pulse, which is easily achieved by inserting a resistor between the output of U2 and the gate of Q1.

We will not do that just yet. Instead, we will use this as an opportunity to investigate the use of decoupling or bypass capacitors on a solderless breadboard.

In the following, it will be useful to refer to the schematic in part I.


Investigating the Voltage Spikes

When you see either vertical spikes or ringing on your output, you should check to see if it is also on your supply rails. Setting scope channel 3 to AC coupling and connecting it to the V^+ power rail reveals the following:

Figure 10. Voltage spikes on V^+ rail.

Trace 2:  Square wave out.
Trace 3: V^+ power rail.

This explains the spike on the triangle wave output. At the rising edge of the square wave, the spike is also present on the power rail with a peak-to-peak amplitude of about 0.2 V. So it will also be on the input to U1 through the potentiometer R8 and on the op-amp power pin V^+.

Figure 11. A graph of Power Supply Rejection Ratio agaist frequency for the OPA1652 op-amp. (page 7 of datasheet).

The op-amp is ineffective at rejecting high frequency transients. The graph in figure 11 shows that the Power Supply Rejection Ration (PSRR) of the OPA1652 op-amp decreases at a rate of about 20 dB a decade in frequency, reaching 0 dB, i.e. no rejection, at about 40 MHz.

We can estimate the width of the spike by zooming in on the time axis on the scope as in figure 12 below.  It is roughly 100 ns if we ignore the final overshoot and ringing. So the frequency of the first harmonic is about 10 Mhz, resulting in PSRR of only 12 dB ≅ 1/4, which can’t be ignored.

Figure 12. Magnifying the time direction of the trace in figure 10.

So what can be causing them? A clue is that when I tape the battery connector wires together as in figure 13 below, the spikes decrease in amplitude from about 0.2 V to 0.12 V as in figure 14.

Figure 13. Battery leads untaped and taped. Corresponds to the traces in figure 10 and figure 14 respectively.

Figure 14. Shows reduction in voltage spike amplitude compared to figure 10, when the battery leads are taped together.

Trace 2:  Square wave out.
Trace 3: V^+ power rail.
Trace 4: Top ground rail.

Note, we take the bottom ground rail as our 0 V reference.

From this we can infer that they are at least partly caused by ‘parasitic’ self-inductance of the battery wires. There is a sharply changing current in the wires which induces a voltage spike. When the wires are brought close together, the opposing magnetic fields caused by the opposite currents partly cancel, thus reducing the total self-inductance and the induced voltage. This is the only sensible inference.

Reducing voltage spikes by shortening, taping or twisting together wires is only a last resort. For the rest of this post I will not bother to tape them together.

For wire with inductance L, there is an induced voltage proportional to the rate of change of current:

(1)   \begin{equation*}  V = L \frac{dI}{dt} \end{equation*}

It does not matter how small the current is, or how small the inductance. If the current can change quickly enough, there will be a measurable induced voltage.

We can represent the parasitic inductance due to the battery leads as L+ and L-  in the following circuit of figure 15. The voltmeter represents the oscilloscope and the current source the rest of the circuit.

Figure 15. Simplified equivalent circuit showing inductance of power leads .

Using the above equation (1) and the trace of the spike in figure 12, we can deduce the shape of the current-time graph.

A neat feature of the Rigol DS1054Z digital oscilloscope is its ability to export a trace as a CSV file, which you can process in a scientific program such as Mathematica. Here is a Mathematica plot of the voltage spike below:

Figure 16. Voltage spike graph exported as a CSV file to Mathematica

The current comes from integrating equation (1)

(2)   \begin{equation*} \int_0^t{dt' V(t')} = L I(t) - LI(0) = L \Delta I(t) \end{equation*}

for known inductance L=L^+ + L^- \approx 325 \text{nH} (measured using a cheap and nasty digital signal generator and a scope). Although a direct measurement is usually preferable, see here or here for an inductance calculator for wire in various different geometries.

To get V(t), the voltage across the inductance L from the a.c. voltage on the scope in figure 15 and 16, we have to remember to first multiply by -1. I also subtract a constant V(0) from V(t) so we only get the current pulse due to the MOSFET switching on. There is also a more gently increasing current present related to the rising edge of the square wave which causes V(0).

Finally, hey presto! This is what the current pulse looks like:

Figure 17. Current pulse due to MOSFET switching on by integrating figure 16.

Notice the overall increase in current. This is likely to be due to the extra current flowing through the power leads after the MOSFET has switched on.

Let’s see if this graph agrees with what we know about a MOSFET. It switches on when the gate voltage V_{GS} reaches the threshold voltage. There is non-zero capacitance between gate and drain terminals. For V_D to fall from V_{in}/2 to near zero, this capacitance most charge up. According to figure 10 of the 2N7000 datasheet, this requires very roughly \Delta Q_G ≈ (0.8-0.2) nC ≈ 0.6 nC of charge to flow to the gate at the instance it switches on1. So we are expecting a current pulse with average value

(3)   \begin{equation*} <I_G> = \frac{\Delta Q_G}{\Delta t} \approx \frac{0.6 \text{nC}}{100 \text{ns}} \approx 6 \text{mA} \end{equation*}

to flow to the gate. By eye, the average current of the pulse in figure 17 looks to be around 4 mA, so it is in the same ballpark!

Using Decoupling Capacitors on a Breadboard

As mentioned earlier, it is good practice to have the decoupling capacitors work only as hard as they need to, by smoothing out unnecessarily quick changes in current which could cause voltage spikes due to parasitic inductance. We avoid good practice here to put decoupling on a breadboard through its paces!

It is common knowledge by professionals and hobbyists alike that one should use decoupling or bypass capacitors in any circuit to reduce voltage ripple and spikes on the power rails and on the power pins of IC’s. Typically there will be one or more capacitors between each power supply rail and ground and each IC will also have its own decoupling capacitors. Also, typically higher value >10 µF tantalum or electrolytic capacitors are used to smooth lower frequency ripples on the power rails and 0.01 µF to 0.1 µF ceramic capacitors2 are used to reduce higher frequency voltage spikes on power rails and individual IC’s. The exact values used depend on the application.

See here for some application notes on using decoupling capacitors [1, 2, 3, 4].

Decoupling a power rail

There are issues on a breadboard which prevent ideal decoupling. Let’s see what happens to the voltage spikes when I place a 33 μF tantalum capacitor between 9 V and ground as in figure 18 below. The generic IC represents the rest of the circuit.

Figure 18. Breadboard with generic IC and a tantalum decoupling capacitor.

I have used the impressive and free Fritzing package to make the above graphic. It is natural to use the top and bottom rails as 9 V and 0 V respectively since this follows the typical layout of a schematic and the V^+ and ground power pins are on opposite sides of the IC usually.

Figure 19. Reduced voltage spike on the V^+ power rail using a 33 μF decoupling capacitor

Trace 2:  Square wave out.
Trace 3: V^+ power rail.

As you can see, the spikes are reduced from a peak-to-peak amplitude of about 200 mV to 40 mV, which is an improvement but hardly ideal. If we now add a 0.1 μF and a 0.01 μF ceramic capacitor in parallel and right next to the tantalum, the spikes are reduced slightly further to 33 mV as seen below, but still no cigar!

Figure 20. Spikes on V^+ and top ground rail with 33 μF, 0.1 μF, 0.01 μF decoupling capacitors in parallel.

Trace 2:  Square wave out.
Trace 3: V^+ power rail.
Trace 4: Top ground rail.

What is more, the top ground rail also has spikes which add to the misery. Note, without the capacitors, there was a negligible signal on the top ground rail as in figure 14.

In fact, the signal on the top ground and the 9 V rail is almost identical, which means firstly that the voltage across the capacitors which is the difference between trace 3 and 4 is much smaller than 33 mV and secondly, that most of the voltage spike is across the wire which connects the two ground rails as seen in figure 18. This wire acts as an inductor Lgnd in the below LC voltage divider.

Figure 21. Equivalent circuit for the breadboard layout of figure 18 with the wire connecting the two ground rails represented as Lgnd and the battery wires  as L+ and L-.

At high enough frequency f, the magnitudes of the impedances obey

(4)   \begin{equation*} \left |Z_{Lgnd}\right | >> \left |Z_C\right |, \end{equation*}

where C= C_1 + C_2 as is the case here, since \left |Z_{Lgnd}\right | \propto f and \left |Z_C\right | \propto 1/f , ignoring parasitic inductance in the capacitor packages. Lgnd and C act as a voltage divider, with most of the voltage spike across Lgnd, hence explaining the above observation that the top ground rail and V^+ having a similar voltage trace.

Indeed, the inductance of copper wire with diameter 0.6 mm and length 4.5 cm is about 40 nH using an inductance calculator. So, we can naively estimate the impedences3 at f= 10 MHz as

(5)   \begin{eqnarray*} \left |Z_{Lgnd}\right |\simeq 2.5 \Omega &&  \left |Z_{C}\right | \simeq 0.48 \times 10^{-3} \Omega \end{eqnarray*}

using the usual impedance formulae Z_L = j 2\pi f L and Z_C = 1/(j 2 \pi f C).

This is a nice demonstration of why we want to minimise wire or trace length and thus series inductance and impedance between the decoupling capacitors and ground. The induced voltage across Lgnd is responsible for the residual spikes in figure 20.

As a solution, we could take the approach of simply not using the bottom ground rail thus effectively removing Lgnd as below:

Figure 22. Without using the bottom rail, there is better decoupling of the power rail, but it leads to longer and inconvenient connections from the bottom half of the board to ground with higher inductance.

However, the length of the connection from the ground pin of the IC to the ground rail is increased, as is its inductance, leading to increased ground pin spikes. In general, all connections from the bottom half of the board to ground are both inconvenient and with increased inductance. This is an annoying issue for breadboards.

We want to keep both ground rails as in figure 18, but reduce Lgnd so that \left |Z_{Lgnd}\right | << \left |Z_C\right |. The length of the connection is fixed at 4.5 cm.

I propose a solution as explained in a future post, which is to hack the board Blue Peter style! We can make a much lower inductance connection between the ground rails by using aluminium foil strips connecting underneath. This works by increasing the effective diameter of the connection.

Figure 23. Low inductance connection between ground rails underneath the breadboard, Blue Peter style!

This is a sort of a ground plane in a very loose sense. Let’s see how our newly hacked breadboard behaves, with the same set-up as for figure 18, but now there is no need to connect the ground rails on top of the board.

Figure 24. Reduced voltage spikes with the hacked breadboard compared to figure 20.

Trace 2: Square wave out.
Trace 3: V^+ power rail.
Trace 4: Top ground rail.

Note the more sensitive scale. Crucially, from figure 24 we see that the voltage across the ground connection Lgnd has reduced from 33 mV as in figure 20 to about 2 mV and the spike on the V+ rail has reduced from 33 mV to 6 mV peak-to peak. We can deduce from this that the impedance of the connection is now about a quarter of the impedance of the capacitor, when previously it was much more. This is a triumph for Blue Peter style hacking and although not as good as can be expected on a well designed 2-sided PCB with a real ground plane, it is much more acceptable!

Decoupling the power pins of an IC

As mentioned before, for high frequency spikes, we should also decouple IC’s separately. Let’s see why:

Figure 25 below shows the reduced voltage spikes on the V^+ rail right near the decoupling capacitors.

Figure 25. Decoupled V^+ rail near decoupling capacitors.

Trace 1: Triangle wave out.
Trace 2: Square wave out.
Trace 3: V^+ power rail.

Let us compare this to V^+ on the power pin of the op-amp IC:

Figure 26. Increased voltage spike on V^+ pin of op-amp

Trace 1: Triangle wave out.
Trace 2: Square wave out.
Trace 3: V^+ power pin on op-amp.

The amplitude has increased from about 1.5 mV to 7.5 mV. Why? Because the 100 ns current pulse passes from the power rail to the V^+ pin, then to the output pin of U2 and directly to the MOSFET gate. The connection between the decoupling capacitors and the V^+ pin consists partly of wire and partly breadboard track as shown by the magenta line in figure 27 below.

Figure 27. Shows signal path from decoupling capacitor to the IC.

It has an inductance which I have measured as roughly 15 nH. By comparing to figure 16, I would expect a voltage peak-to-peak amplitude of about 15 nH/325 nH × 200 mV  ≈ 10 mV (to 1 sig. fig.), which is consistent with the above trace. This is normal, and a nice demonstration of why individual IC’s need decoupling capacitors.

There are various options for decoupling, none of which are ideal due to the connection length of about 2 cm between the V^+ pin and the top ground rail. (Assuming a hacked board with insignificant inductance between the two ground rails.) This can lead to a series inductance of around 15 nH  for a connection with effective diameter 1 mm. Nevertheless, let’s see what happens when I connect a 0.01 µF ceramic capacitor from the V^+ pin to the top ground rail as in figure 28 below.

Figure 28. This illustrates non-ideal decoupling of V+ pin of an IC. The green signal path acts as an inductance in series with the blue decoupling capacitor from the pin to the ground rail.

Figure 29. The reduced voltage spike on the op-amp V^+ pin after decoupling.

Trace 1: Triangle wave out.
Trace 2: Square wave out.
Trace 3: V^+ power pin on op-amp.

The spike on the op-amp power pin has dropped from around 7.5 mV to 4.5 mV, but it is still more than the spike on the rail due to the extra parasitic series inductance. Here is an equivalent circuit:

Figure 30. Equivalent circuit showing non-ideal decoupling of the V+ pin due to series inductance Lseries caused by a long signal path to ground.

On a two sided pcb, the decoupling capacitor would be mounted no more than a few mm’s from the V^+ pin and would connect to the ground plane below with a via using a much smaller signal path.


We have seen how a current pulse of time period about 100 ns, caused by the MOSFET switching on, induced voltage spikes on the V^+ power rail, due to the inductance of the power leads. These undesirable spikes also appear on the output of the VCO.

We reproduced the current-time graph of the pulse by numerically integrating the a.c. component of the supply rail voltage V^+  against time using Mathematica.

We saw that the breadboard is also a nice tool for demonstrating the pitfalls of using a too long path length from decoupling capacitor to ground. With a connection of about 4.5 cm long (the distance between the ground rails) the decoupling capacitors only reduced the spikes from 200 mV to about 33mV due to the series inductance of the wire Lgrnd.

By crudely hacking the breadboard, we were able to make a low inductance connection between the top and bottom ground rails. This allowed effective decoupling of the V^+ rail while maintaining equal use of both ground rails. The spikes were reduced from 200 mV to 2 mV amplitude peak-to-peak.

Decoupling of an individual IC was less successful, due to a minimum path length of the V^+ pin to ground of about 2 cm, resulting in significant series inductance. Nevertheless, the decoupled V^+ pin still had spikes of only 4.5 mV. This suggests that if you don’t care about a few mV’s of ripple, parasitic inductance need not be an issue on a carefully decoupled breadboard for frequencies up to 1/(100 ns)  ≈ 10 MHz.

Let’s see the trace of the triangle wave now and compare it to the undecoupled version in figure 7 here.

Figure 31. The triangle wave with decoupled power supply.

The spike on the triangle wave is no longer visible by eye, but the bottom vertex is more pointed. Also, the square wave still has the bump where the MOSFET switches on and we haven’t addressed the other issues mentioned in part I.

The adventure continues…!

[1] P. Brokaw, “An IC Amplifier User’s Guide to Decoupling, Grounding, and Making Things Go Right for a Change,” Analog Devices AN-202.
[Link] [Bibtex]
title={{An IC Amplifier User’s Guide to Decoupling, Grounding,
and Making Things Go Right for a Change}},
author={Paul Brokaw},
address={Analog Devices AN-202},
[2] “Decoupling Techniques,” Analog Devices MT-101 Tutorial.
[Link] [Bibtex]
title={{Decoupling Techniques}},
address={Analog Devices MT-101 Tutorial},
[3] T. Schmitz and M. Wong, “Choosing and Using Bypass Capacitors,” Intersil AN-1325.
[Link] [Bibtex]
title={{Choosing and Using Bypass Capacitors}},
author={Tamara Schmitz and Mike Wong},
address={Intersil AN-1325},
[4] T. Tran, “OMAP5910 Decoupling/Filtering Techniques,” Texas Instruments SPRA906.
[Link] [Bibtex]
title={{OMAP5910 Decoupling/Filtering Techniques}},
author={Thanh Tran},
address={Texas Instruments SPRA906},
Posted in Oscillator, Solderless Breadboard, Troubleshooting | Tagged , , , , | Comments Off on A Square and Triangle Wave VCO. Part II – Taming the Voltage Spikes.

A Square and Triangle Wave VCO. Part I

As a first circuit to write up, I have chosen a clever little schematic for a triangle and square wave Voltage Controlled Oscillator (VCO) from section 4.29 of what I affectionately call the large silver door-stopper: ‘The Art of Electronics 2nd ed.’ [1]. This in turn was taken from ‘the application notes of several manufacturers’  [a reference anyone?]. It is notable as most VCO‘s and indeed op-amp circuits are dual supply. On the surface, it is fun and simple for someone who understands the basics of op-amps, resistors and capacitors, but sufficiently rich that enough things can go wrong to make it interesting!


A function generator is a must-have in every electrical engineer’s and hobbyist’s toolkit. These days, generators which use Direct Digital Synthesis (DDS) are the norm. They typically have superior stability and accuracy. However, a good one is not that cheap, so why shell out when you can build a basic, analogue Voltage Controlled Oscillator (VCO) yourself for peanuts, in just a few minutes on a solderless breadboard and learn some skills in the process?

Constructing oscillators in particular is a fun way to quickly experience some common pitfalls in putting analogue circuits which look good on paper into practice. Any misbehaviour is usually immediately clear on the oscilloscope trace.

I intend to use the below circuit as a vehicle to troubleshoot some “unexpected” problems due to the non-ideal behaviour of certain components including the breadboard itself. I use quotation marks, but the first time I built this circuit, they really were unexpected!

The Circuit

Schematic version 0.9

Figure 1. Single supply triangle VCO version 0.9.

R1-R7: Metal Film 0.25 W ±1%, e.g. Multicomp MF25
R8: Potentiometer, e.g. vertical preset TE CB10.
C1:  1 nF ±5% Film capacitor, e.g. WIMA FKP2.
U1, U2: Rail-to-rail, dual op-amp, e.g. OPA1652.
Q1: n-channel MOSFET e.g. 2N7000.
BT1: 9V PP3 battery e.g. Duracell MN1604.


I am using a 9V PP3 battery as a simple, cheap power supply option. V^+ and V^- on the op-amp are connected to +9 V and 0 V respectively.

The triangle wave varies between 1/3 V^+ and 2/3 V^+ and the square wave switches between 0 and V^+. Of course you can pass them each through a single stage RC high-pass filter to get an a.c. output or add further op-amps to change voltage offset and amplitude.

To work as mathematically required we simply need R1=2R4, R2=R3 and R5=R6=R71. In this case, the frequency is given by:

(1)   \begin{equation*} f=\frac{3}{4} \frac{1}{R_1 C_1} \frac{V_{in}}{V^+}= 75\frac{V_{in}}{V^+}  \text{ kHz}. \end{equation*}

V_{in} varies between 0 and V^+, but in fact one can go up to just less than 2 V^+. I have changed some component values from the original schematic to crank up the maximum frequency from 150 Hz to 75 kHz. This will make things more interesting!

I am using pot. R8 as a crude variable voltage source- crude because it has significant output resistance away from V_{out}=V^+ or 0. Because current draw through the V_{in} connection should not change with time at a given frequency, a voltage follower op-amp buffer should not be needed and V_{in} should not dance around.

Because frequency depends only on the ratio V_{in}/ V^+ which in turn only depends on the wiper position in a pot. voltage divider, the output frequency will be independent of V^+. This is useful, since if V^+ comes from a battery, it will decrease significantly over time, without affecting the frequency.


Op-amp U1 acts as an integrator, U2 as an inverting Schmitt Trigger and the n-channel MOSFET Q1 as an analogue switch which is controlled by the output of U2.

R2 and R3 act as a voltage divider, setting the positive op-amp input

(2)   \begin{equation*} V_{in1}^+ =\frac{V_{in}}{2}. \end{equation*}

We use the principle that an ideal op-amp with negative feedback will instantly adjust its output voltage such that V_{in1}^+ =  V_{in1}^-. When the output of U2 is high, Q1 is on and R4 is effectively connected to ground. A few calculations reveal that the current though the capacitor is given by I_{C_1} = V_{in}/2R_1 when the MOSFET switch is open and by I_{C_1} =- V_{in}/2R_1 when the switch is closed, assuming the MOSFET has a neglibile on-resistance.

U1 integrates the (constant) current I_{C_1} as

(3)   \begin{equation*} \Delta V_{out1} = -\frac{I_{C_1}}{C_1} \Delta t, \end{equation*}

for change in time \Delta t, producing the falling or rising edge of the triangle wave when the MOSFET switch is open or closed respectively.

Now for U2: in a positive feedback configuration, the op-amp acts as a comparator with the feedback causing some hysteresis. Note resistor R7 is effectively in parallel with R6 when the output V_{out2}= V^+ and in parallel with R5 when V_{out2}=0. The resultant voltage divider leads to the 1/3 V^+ and 2/3 V^+ trigger points and the following behaviour:

Rendered by QuickLaTeX.com

Figure 2. U2 Schmitt trigger: graph of V_{out2} against V^-_{in2}.

Put it all together and you get a triangle wave from V_{out1} and a square wave from V_{out2} as follows:

Rendered by QuickLaTeX.com

Figure 3. The expected voltage output.

So what could possibly go wrong?



Figure 4. Breadboard for VCO ver. 0.9

Note the black wire on the left, which I have used to connect the two ground rails together.

If you don’t own a lab supply, a 9V PP3 battery is a good way to go. It is cheap and low noise and not connected to earth, so there can be no ground loop problems. The disadvantages are that internal resistance is relatively high: 0.8 Ω, and the Voltage fades with time to about 7 V after 60 hours with a 1000 Ω load.

To set R4 as 5 kΩ I used two 10 kΩ resistors in parallel, since 5 kΩ resistors are not common.

I’m using a preset trimmer rather than a full potentiometer, as these fit conveniently into the breadboard. Vertical presets only take up 3×2 holes of space.

I have found that ‘rail-to-rail’ op-amps are hard to come by in a DIL package. Instead, I have used an OPA1652 surface mount IC, which I soldered onto a 4×2 SOIC to DIP adapter. I then soldered on some 0.1″ header as in figure 5 below, and it slots nicely into the breadboard. This op-amp is a bit fancy for purpose- I was planning to use it for an audio pre-amp, but it’s not too expensive.


Figure 5. Before and after: A SOIC to DIP adapter board, some 0.1″ header and the OPA1652.

A tip: before soldering the header to the adapter board, I mount them in an old unwanted breadboard. This keeps the headers nice and aligned when I solder them in place. Heat will damage the breadboard, so don’t use your best one!

See here and here for some tips on surface mount soldering.

The only issue, is that this particular adapter uses up an extra two rows of holes compared to a DIP IC when inserted in the breadboard.

First Measurements

Let’s try at a fixed frequency, with V_{in}=V^+.


Figure 6. Output of VCO version 0.9.

Trace 1: Triangle out (V_{out1}).
Trace 2: Square out (V_{out2}).
V_{in}=V^+ = 7.7 V

Note, first that it basically works! However, the waveforms aren’t as ‘clean’ as they should be. See the spike at the bottom tip of the triangle wave below:

Figure 7. Triangle wave detail. Note the spike at the bottom tips.

If we magnify the time direction, we can also see a bump on the rising edge of the square wave:

Figure 8. Artefact on the rising edge of square wave.

The frequency is lower than the expected 75 kHz even taking into account the ±5% capacitor tolerance.

For really small V_{in}= 21 mV, the triangle wave is no longer symmetrical:


Figure 9. Unsymmetrical output for small V_{in}=21 mV

This is not ideal!

The adventure is just beginning, so let’s investigate further!

To be continued….

[1] P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., Cambridge Univ. Press, 1989.
[Link] [Bibtex]
title={{The Art of Electronics}},
author={Horowitz, Paul and Hill, Winfield},
publisher={Cambridge Univ. Press},
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I hereby declare that I will endeavour…

  1. To build only cool and interesting circuits.
  2. Using cheap, readily available components.
  3. With the simplest, most elegant design and the fewest components possible.
  4. And the nicest possible relevant properties, for example in an oscillator, stability with temperature and time, nice clean waveforms, low distortion etc..
  5. With no excessive power consumption.
  6. With small physical circuit size: no bulky components.
  7. And with as few preset resistors to adjust as possible (ideally none).
  8. The design has to be forgiving of component behaviour within advertised tolerances and especially doesn’t depend on specific values of unreliable quantities such as h_{FE} for a transistor.
  9. I will also avoid relying on hand-matched pairs of components where possible.
  10. I will test the circuit on a real solderless breadboard, or some other prototype board for high frequency/current (no circuit simulators), and push it to extremes to find where its limitations are and any departure from ideal behaviour. For example, with a variable frequency oscillator, I will find what limits its maximum and minimum frequency and why.


All subjective terminology such as cool, cheap, elegant, low power and small are determined by me of course, but to give you an idea: I think even a humble relaxation oscillator can be cool, a £10 capacitor is ultra-expensive, a battery powered circuit which lasts only 1 hour is a power monster and a dual-gang variable capacitor is likely to be bulky.

I reserve the right to renege on all of the pledges numbered 2 to 9 in the name of pledge number 1.

What would you add to this list?

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